The present invention relates to semiconductor devices, and more particularly to semiconductor devices and methods for improving the current carrying capability of semiconductor devices having a stripe geometry pattern on a surface thereof.
Semiconductor devices, and more particularly metal oxide semiconductor (MOS) devices used in power applications, are operated when an electric potential is applied across a drain and a source and a voltage is applied to a gate to control current flow between the drain and the source. With reference to FIG. 1, electron flow in such semiconductor devices 10 of the prior art is from a source region 12, laterally through a channel region 14 (formed in the depletion region under the gate electrode 16), to a neck region 18 and vertically to the drain 20.
Semiconductor devices 10 of the prior art include a wafer with a silicon region 24 of a first semiconductor type. Well regions 26 of a second semiconductor type are patterned and implanted and/or diffused into the silicon region 24. Within each of the well regions 26 are patterned source regions 12 that do not extend into the silicon region 24. The edges of the well regions 26 and source regions 24 form the channels 14. The edges of the well regions 26 define the boundaries of the stripe geometry pattern. Portions of the well region 26 are masked when the source regions are formed so that the masked portions are excluded from the source region doping. These source exclude areas 28 provide locations for contact of the well regions 26 with the device source metal 30. A gate oxide layer is formed over both the neck regions 18 and the channel regions 14, and a polysilicon layer 16, which serves as the gate electrode, is deposited over the gate oxide regions.
As may be seen more clearly in FIG. 2 that is a plan view of the surface 22 of a semiconductor device of the prior art with the gate oxide, gate and source metal removed, the source exclude areas 28 are placed directly across from each other in adjacent source regions 12. As a result of this design, the lateral current flow in the surface of the device from the source regions 12 to the neck regions 18 does not have a uniform density. As may be seen by the dispersion of the arrows in FIG. 2, current density is greatest in the portion of the neck region between opposing source regions 12, and the density is least in the portion of the neck region between opposing source exclude areas 28. In other words, the design of the prior art produces current crowding in portions of the neck region that causes a larger portion of the device current to flow laterally to the portions 34 of the neck regions between the source exclude areas 28 and the channel 14, thereby increasing the device on-resistance. As is known, increased on-resistance generally decreases the current carrying capability of the device.
The portions 34 between the source exclude areas 28 and the channels 14 do not conduct as efficiently as the larger areas between source exclude areas 28 because the electron path is longer and the portions have a small cross-sectional area. The resistive voltage drop contributed by increased current flow in region 34 adds to the on-resistance of the device.
Accordingly, it is an object of the present invention to provide a novel device and method for increasing the current carrying capability of a semiconductor device with a striped geometry.
It is a further object of the present invention to provide a novel device in which the source exclude areas in adjacent well regions are offset to increase the uniformity of the current density in the neck regions.
It is yet a further object of the present invention to provide a novel method for enhancing the current carrying capability of a semiconductor device by increasing the uniformity of current density in the neck regions.
It is another object of the present invention to provide a novel method for reducing on-resistance in a semiconductor device by increasing the uniformity of current density in the neck regions.
It is yet another object of the present invention to provide a novel method of reducing on-resistance in a semiconductor device by offsetting source exclude areas in adjacent well regions.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of preferred embodiments.